1. Field of the Invention
The present invention relates to a semiconductor device comprising a silicon pillar formed on a substrate and to a method of manufacturing the semiconductor device.
2. Description of Related Art
With respect to semiconductor memories as one kind of semiconductor device, there has been a demand for reducing the chip area year by year for the purpose of achieving a low cost. To meet this demand, 4F2 (2F×2F) cell structures have been proposed for dynamic random access memories (DRAMs) which is one kind of semiconductor memory. “4F2” means the area of a memory cell which comprises of one transistor and one capacitor, and “F” means the minimum feature size.
In the 4F2 cell structures, a capacitor and a transistor which are included in a memory cell are vertically stacked. FIGS. 1(a) and 1(b) are sectional views showing an example of the structure of a transistor constituting a memory cell of a 4F2 cell structure. The transistor shown in FIG. 1(a) has silicon pillar 101 formed on silicon substrate 100 by etching. A side surface of silicon pillar 101 is covered with gate electrode 103 via gate oxide film 102. When a voltage is applied to gate electrode 103, a channel is produced in silicon pillar 101, and a longitudinal (vertical) current path is formed from silicon pillar 101 to capacitor 105 through upper contact 104.
If the diameter of silicon pillar 101 in the transistor shown in FIG. 1(a) is reduced (silicon pillar 101 is made thinner) as shown in FIG. 1(b), the electron mobility increases with the reduction in density of states of places to which electrons are scattered and, therefore, the transistor can operate at a higher speed. Also, as a result of the reduced size of junction area, the probability of crystal defects contained in silicon pillar 101 is largely reduced and, therefore, the leak current is limited. As a result, the occurrence of minority bits in the DRAM is limited.
However, if silicon pillar 101 is excessively thin, the area of contact with upper contact 104 is so small that it is difficult to establish a low-resistance contact between silicon pillar 101 and upper contact 104. A transistor manufacturing method devised to solve such a problem has been proposed and disclosed in Japanese Patent Laid-Open No. 2008-177573.
In the method disclosed in Japanese Patent Laid-Open No. 2008-177573, a recess is formed in a central portion of a side surface of a silicon pillar by isotropic etching. That is, the silicon pillar has a shape such that only its central portion is made thin. In this way, the silicon pillar can be made thin without reducing the contact area at the top of the silicon pillar.
In the method disclosed in Japanese Patent Laid-Open No. 2008-177573, however, various crystal planes of the silicon crystal are exposed in the side surface of the silicon pillar after isotropic etching has been performed, because the silicon pillar is made thin by isotropic etching. When gate oxide film is formed in such a condition, variation in film thickness occurs due to a plane-direction dependence of the oxidation rate. From this, variations in the characteristics of the transistor (e.g., the threshold voltage and the leak current) can occur. There is, therefore, a possibility that the uniformity of the characteristics of the transistor will be impaired.